Karim Sabra

Organization: CNRS – Institut de Physique des 2 Infinis (IP2I), Lyon

Context: main 5th-year apprenticeship project, still evolving with verification maturity ramping toward ASIC integration.

What I did

• Implemented and integrated the digital core in an ASIC readout chain: clean reset/clear, robust sequencing, safe interfaces, illegal-state protections.
• Built and maintained self-checking SystemVerilog verification components: stimulus, monitors, scoreboards, pass/fail checks, debug-oriented logging.
• Verified streaming FIFO / ready-valid handshakes and sequencing logic, including corner cases and backpressure scenarios.
• Wrote foundational SVA assertions for safety and ordering properties (reset, handshakes, illegal-state protection).
• Ran 10,000+ self-checking simulations across 100+ random seeds in Xcelium, debugged failures via waveforms/logs, and drove fixes with designers.
• Built a Python parsing + data extraction pipeline to track KPIs and support calibration (sanity checks, trends, reporting).

Results (simulation)

• Time precision improved: ~20 ps RMS → ~8 ps RMS.
• TDC dead time reduced: ~80 ns → ~40 ns.

Goal

• Drive an end-to-end flow RTL → verification → calibration → sign-off KPIs → integration → tape-out, with reproducible regressions and traceable criteria.

Deliverables

Internal detailed docs and reports available on request. (Public repo: pending.)

Context: Wrap-up project across digital design, embedded Linux, RTOS, networking, and cloud. Breadth over depth by design.

What I did

• Integrated VexRiscv RV32IM on Nexys A7-100T. Manual Linux boot. Brought up Ethernet and a lightweight UDP protocol to exchange plate events with BeagleY-AI.
• On BeagleY-AI, flashed TI Edge AI SDK. Configured IMX219 pipeline with tiovxisp and multiscaler. Used TIDL models on DSP cores for plate detection. Tuned buffers and caps for stable real-time throughput.
• Wrote the FPGA side FSM in Verilog to drive barrier outputs on event receipt. Added a stub for stepper motor stages and door interlocks.
• Produced camera bring-up notes, latency measurement script, and a minimal telemetry frame over UDP for debugging.

Results

• Real-time streaming and detection on DSP cores with stable Ethernet handoff to the FPGA.
• Barrier FSM actuates on validated plate events from BeagleY-AI.

Deliverables

Repo and docs pending.

Next

• Client database, billing workflow, RFID entry, stepper control for camera tilt and door, sensor matrix, and LCD status panels.
• Ops dashboard, remote override, OTA updates, logging, and cyber hardening.

Context: Academic FPGA project covering metastability, FSM design, and serial communication in VHDL.

What I did

• Metastability study with synchronizers and timing checks.
• Stepper motor driver FSMs, tested with 28BYJ-48 + ULN2003.
• Clock divider for speed control and module sync.
• UART TX/RX, baud generator, oversampling, loopback tests.

Results

• Stronger digital design and FPGA prototyping practice.
• FSMs validated in simulation and hardware.

Deliverables

Full Report (FR, PDF)

Context: Clean-room fabrication, analog circuits, and PCB prototyping.

What I did

• Clean-room steps: photolithography, spin-coating, UV exposure, metal deposition.
• Analog conditioning circuits with op-amps.
• PCB in KiCad, hand-soldered, full chain assembled.
• STM32 drivers, timers OK, ADC partial.

Results

• Complete microsensor workflow from fabrication to validation.
• Operational analog front-end, partial digital acquisition.

Deliverables

Poster presentation (FR, PDF)

Context: Skill building in RTL, verification, and computer architecture.

What I did

• Single-cycle RV32I datapath in SystemVerilog: control, ALU, sign-extend, register file, instruction and data memory.
• Typed opcodes and ALU control enums. Byte-enable memory and load-store decoder.
• cocotb tests for units and top-level with randomized ALU checks.
• Prep for SoC work with clean interfaces and a small config package.

Results

• Core runs basic programs in simulation. ALU, loads, stores, branches, and partial loads pass current tests.

Credits

Following “The HOLY CORE project, A full RISC-V RV32I Core Tutorial, Single cycle edition”.

Deliverables

Repo and docs pending.

Organization: CNRS – Institut de Physique des 2 Infinis (IP2I), Lyon

Context: Second apprenticeship year, fourth diploma year

What I did

• Migrated PLL from TSMC 130 nm to TowerJazz 180 nm.
• Resized transistors and redesigned loop filter.
• Spectre simulations of PFD, charge pump, VCO, divider, and full loop.
• Validated lock time 1.5–2 µs, jitter ~2 ps RMS, stable 160 MHz.
• Layout: floorplanning, guard rings, parasitic extraction.
• Post-layout: 2.58 GHz VCO, jitter 7 ps.

Results

• PLL validated and integrated in PICMIC-1.
• Stable 160 MHz clock.
• Autonomy in analog layout and verification.

Deliverables

Full 4th Year Report (FR, PDF)

Organization: Instituto de Microelectrónica de Sevilla (IMSE-CNM, CSIC/US)

Context: International internship under Dr. José M. de la Rosa

What I did

• Reviewed CT ΣΔ theory, OSR, SNR, SNDR, ENOB.
• Parametric sweeps on Active-RC and Gm–C with Spectre/OCEAN.
• Unified OCEAN automation script.
• Python GUI in Tkinter to manage sweeps.
• Datasets for ML use with plots.

Results

• Reusable flow across topologies.
• Clean datasets for training.
• Improved handover with GUI and reports.

Deliverables

Internship Report (EN, PDF)